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Processing Instruction
Results: 1077

#	Item
61	RISC-V on Sakura-G Advisor(s): Thomas Unterluggauer Institute for Applied Information Processing and Communications (IAIK) Graz University of Technology, Austria Motivation Add to Reading List Source URL: www.iaik.tugraz.at Language: English - Date: 2015-09-08 06:00:03 Instruction set architectures Reconfigurable computing Fabless semiconductor companies Xilinx Field-programmable gate array RISC-V Reduced instruction set computing
62	Paper Title (use style: paper title) Add to Reading List Source URL: mesl.ucsd.edu Language: English - Date: 2012-04-03 01:39:08 Central processing unit Microprocessors Microcomputers Telecommunications engineering Clock signal Instruction set
63	Chapter 1 Performance Measures Reading: The corresponding chapter in the 2nd edition is Chapter 2, in the 3rd edition it is Chapter 4 and in the 4th edition it is Chapter 1. When selecting a computer, there are differen Add to Reading List Source URL: eceweb.ucsd.edu Language: English - Date: 2015-07-31 19:30:10 Central processing unit Clock signal Computer performance Instruction set architectures Cycles per instruction Rates MIPS instruction set Instructions per second Clock rate CPU time Protection ring Computer
64	T9000 - superscalar transputer Richard Forsyth Bob Krysiak Roger Shepherd INrvl0S Limited - SGS-Thomson Microelectronics Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:44:50 Central processing unit Stack machines Microprocessors Parallel computing Transputer Computer architecture Processor register CPU cache IDL Instruction set
65	Advanced Parallel Architecture Annalisa Massini Vector architecture 2 Add to Reading List Source URL: twiki.di.uniroma1.it Language: English - Date: 2015-04-28 17:33:30 Central processing unit Parallel computing Computer architecture Supercomputers Instruction set architectures Processor register Cray-1 MIPS instruction set SIMD Instruction set 64-bit computing Euclidean vector
66	Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2015-12-01 06:21:41 Instruction set architectures Central processing unit Computer architecture Memory management Memory protection Capability-based security Pointer MIPS instruction set 64-bit computing Instruction set Reduced instruction set computing Kernel
67	Virtual Machine Showdown: Stack Versus Registers Yunhe Shi, David Gregg, Andrew Beatty M. Anton Ertl Department of Computer Science Add to Reading List Source URL: www.usenix.org Language: English - Date: 2005-08-02 11:12:30 Central processing unit Assembly languages Java virtual machine Android Programming language implementation Stack machine Java bytecode Dalvik Instruction set Processor register Stack Opcode
68	Stratified Synthesis: Automatically Learning the x86-64 Instruction Set Stefan Heule Eric Schkufza Add to Reading List Source URL: raw.githubusercontent.com Language: English Instruction set architectures Central processing unit X86 instructions X86 architecture Computer architecture X86 Instruction set Processor register ARM architecture Low-level programming language NOP Intel
69	Data Sheet PRELIMINARY December 2010 AR9331 Highly-Integrated and Cost Effective IEEE 802.11n 1x1 2.4 GHz SoC for AP and Router Platforms Add to Reading List Source URL: www.openhacks.com Language: English - Date: 2013-10-03 09:25:08 Interrupts Instruction set architectures Management Data Input/Output Central processing unit Universal asynchronous receiver/transmitter IEEE 802.11n-2009 IEEE 802.11 Control register MIPS instruction set
70	Insight into Application Performance Using Application-Dependent Characteristics Waleed Alkohlani1 , Jeanine Cook2 , and Nafiul Siddique1 1 Klipsch School of Electrical and Computer Engineering, Add to Reading List Source URL: www.dcs.warwick.ac.uk Language: English - Date: 2014-11-13 12:51:32 Cache Central processing unit Computer memory Computer architecture Parallel computing CPU cache Locality of reference Benchmark Microarchitecture Instruction set Instruction-level parallelism Draft:Cache memory

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